Senior DFT Engineer (copy)

We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with RTL and PNR design team to drive testability is a key feature of this role!QualificationsHands-on expertise with commercial test generation tools for large complex designsStrong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST and LBISTExperience generating test patterns and analyzing and debugging test failuresExperience with RTL simulation, synthesis and back end implementation flowsExperience defining and implementing stuck-at and at-speed techniquesExperience running test compression flowExperience trading off test options with product performance and schedule requirementsExperience creating and releasing full test programs for device screeningResolve design and flow issues related to DFT, identify potential solutions, and drive executionEducation and ExperienceB.E./B.Tech./M.E./M.Tech in VLSIMinimum of 5 years of working experience in DFT flow of a product company.Strong fundamentals in digital ASIC design, experience with ASIC test, DFT, and debugDetailed Responsibilities and SkillsDefine DFT strategy and methodologiesCreate test vectors, simulate in various modesCollaborate with physical design team to close requirementsValidate DFT requirements are being metWork with designers to increase test coverage, debug observability and flexibilityVerify post-PD designs meet DFT requirementsKnowledge of full DFT flow (test structure insertion, pattern generation, simulation)Hands-on experience with Cadence Genus, Modus toolsShould have good understanding of Verilog/VHDLExposure to low power techniquesKnowledge of TCL and Python scripting is a must #J-18808-Ljbffr